A component pin that isn't connected to any wire or touching pin, and has no no-connect marker.

Unconnected pins are the classic "board arrives dead" mistake.

Two pins whose electrical types shouldn't share a net, judged against a pin-type compatibility matrix. This check reports at two severities: error when two genuine drivers are fighting on one net, and warning when the pairing is merely unusual. Only the error tier moves the score — the warning tier is left at zero on purpose, because measured across our test boards every warning-tier finding was one a competent reviewer would wave through. Findings that recur across several nets because of one design decision are grouped into a single finding rather than repeated.

Two active drivers on one net can short and burn silicon at first power-on. The warning tier is worth a second look, but it is often intentional.

A net with only one pin on it, or a wire segment touching no pins at all.

Usually a connection you think exists but doesn't.

An input pin sharing a net with nothing that could drive it — no output, bidirectional, passive or power pin anywhere on the net, and no pull resistor. Nets that touch a connector are excluded, because on a carrier or module board the real driver legitimately lives off-board where the schematic can't see it.

The pin never sees a defined level, and nothing in the drawing says what was meant to set it.

Two different named power rails (e.g. VCC and 3V3) shorted onto the same net.

Shorted supplies means a fried board, not a debug session.

An electrolytic or tantalum capacitor with its positive terminal on ground and its negative terminal on a live rail. Judged only when one terminal is confidently ground and the other confidently isn't — a cap sitting between two unsigned rails can't be judged from a schematic alone and is left silent rather than guessed at. Scoped to the one polarity convention we verified against real boards; a vendor's own polarised-cap symbol is skipped rather than assumed to number its pins the same way.

A reverse-biased electrolytic heats, vents, and occasionally worse. This one is physical, not a wiring nit.

A single 2-pin resistor with each of its pins on a different named power rail, where both names parse to a real and genuinely different voltage. Ferrites and inductors are excluded — bridging two same-voltage rails for noise filtering is a standard pattern — and if either rail name can't be resolved to a voltage, this stays silent rather than guessing whether it's the same rail under another name.

Meaningful current flows trying to equalise two regulated rails, and the lower-voltage domain's parts absorb it.

An IC power pin sitting on a supply rail that has no capacitor on it anywhere. Fires on total absence only, never on a caps-per-pin ratio — how many a rail needs is a layout-proximity question a schematic genuinely cannot answer, and a ratio rule would fire on well-designed boards constantly.

A rail with nothing across it sags the moment the part starts switching.

A logic input whose only company on the net is a mechanical switch, with no pull resistor. Scoped to input pins, plus bidirectional pins belonging to a dedicated GPIO-expander part with no internal pull of its own. A general-purpose MCU's bidirectional pin is deliberately excluded: reading a button straight off one, using the chip's internal pull-up, is a completely standard working design.

The level is defined while the button is held and undefined the rest of the time.

A bus that looks like I2C with no pull-up resistor on it. "Looks like I2C" is judged from the net's own hand-typed label first — the designer's stated intent for that specific connection — and only falls back to a connected pin's library-defined name as secondary evidence. A pin name that is mode-dependent (e.g. "SCL/CCLK" on a codec that can also speak SPI) doesn't count as evidence on its own.

I2C drivers are open-drain: with no pull-up the line never returns high and no transfer on the bus completes at all.

A passive crystal with no load capacitor on one of its terminals. Presence only — whether the value is right depends on the crystal's own specified load capacitance and the board's stray capacitance, which needs a datasheet. Active oscillator modules are excluded; they're told apart by having a power pin.

Without load caps the oscillator may not start, and that takes the whole MCU with it.

Input pins left completely unconnected and not marked no-connect, grouped one finding per component. Narrower than ERC001 on purpose, because it's a different problem with a different fix: an unconnected output is harmless, an unconnected input is not.

A CMOS input with nothing driving it sits near mid-rail, self-oscillates, and draws extra supply current.

An in-BOM component with no footprint assigned. KiCad flags this when you move to layout — here it's caught while you're still in the schematic.

Layout can't place a part that has no footprint.

The same reference designator (e.g. R5) used on two different components. The same reference on different unit numbers is a multi-unit part — a dual op-amp, a connector split across sheets — which is entirely legitimate and is not flagged.

BOM, pick-and-place, and layout all break when two parts claim one name.

A sub-sheet file this design references couldn't be loaded — missing from the upload, unreadable, malformed, or a circular reference back to one of its own ancestor sheets.

A sub-sheet that fails to load means everything inside it is invisible to the rest of the analysis — the score and results only cover what actually parsed.

A sheet's boundary pin has no matching hierarchical label inside its child sheet, or vice versa — the cross-sheet version of ERC001.

A mismatched boundary connection silently drops a signal at the exact seam between two sheets.

Two differently-named labels attached, on the same sheet drawing, to what is electrically one net. This reproduces KiCad's own multiple_net_names finding. Compared within a single sheet only: a hierarchical bus member renamed at a parent/child sheet boundary is real, intentional KiCad practice and is not flagged.

Which of the two names ends up in the netlist comes down to label-kind priority the designer very likely never meant to invoke.

A global label that connects to exactly one component pin. This reproduces KiCad's own isolated_pin_label finding. Scoped to global labels: a project-wide name reaching only one pin is a stronger signal than a same-sheet local label doing the same, so local labels are excluded on purpose.

Either a stale leftover, or the visible half of a connection that was never actually wired.

A raw power inlet with no reverse-polarity protection part (a diode, a MOSFET) on the same net.

Worth a look, not a verdict: protection is sometimes deliberately omitted on a keyed connector that physically cannot be reversed.

A raw power inlet with no fuse or resettable PTC in line.

Worth a look, not a verdict: an upstream supply that is already current-limited is a real reason to leave one out, and the schematic doesn't show what's upstream.

A USB connector's own D+/D− pair with no ESD or TVS part anywhere on either line. Scoped to USB specifically rather than to connectors in general: a broader version fired mostly on ordinary Qwiic/STEMMA/Grove I2C headers that real professional boards ship without ESD parts, which is not a defect.

Worth a look, not a verdict: some designs deliberately rely on the downstream PHY's own built-in ESD tolerance. USB is singled out because it is routinely a bare cable to an unknown host in the field.

A relay, solenoid or motor coil with no diode on its net. Scoped to those parts specifically and not to inductors in general — the inductor in a switching regulator is the most common one on any board and correctly has no flyback diode across it.

The coil's collapse spike punches straight through whatever transistor was switching it.

A plain 2-terminal LED with no series resistor anywhere on its non-ground net. Addressable RGB LEDs are excluded — they're integrated driver ICs with their own internal current source, not bare diodes — and a default-bridged solder jumper one hop away is treated as electrically transparent, so a resistor sitting on the far side of one still counts.

An LED wired straight across a rail draws whatever the rail allows, usually far past its rating, and can take the pin driving it along with it.

BGA, WLCSP, LGA, BTC, 0201, and 01005 packages are always flagged — the pads aren't side-accessible no matter how fine or coarse the spacing is. QFN/DFN (and vendor variants — VQFN, UQFN, WQFN, DHVQFN, XDFN, …) are pitch-gated: flagged only at 0.4mm lead pitch or finer, parsed directly from the footprint name; coarser QFN/DFN packages (0.5mm, 0.65mm, …) are left unflagged as hand-solderable with a fine-tip iron. A 2-pin QFN/DFN (common on ESD diodes) is treated as a leadless chip-scale part, same class as 0201, since "pitch" doesn't describe a 2-pad part. If a QFN/DFN footprint doesn't state its pitch at all, it's still flagged — with a note that the pitch needs manual verification — rather than silently skipped.

Know you need hot air or reflow before ordering parts — not with an iron in hand.

A part's own SWD/JTAG debug pins exist in this schematic but none of their nets reach any connector. Matched on the pin's library-defined name, never on a net name, and judged coarsely at the "does any debug net reach a header" level rather than per signal — on a real board an MCU's SWD reaching a header while an FPGA's JTAG chains through that MCU is a debug-chaining design, not a defect.

Worth a look, not a verdict: some designs genuinely program before assembly, for example a module that arrives pre-flashed.

Components still holding template values like "R", "C", "~", or nothing at all.

A resistor named "R" becomes a guess at order time. It doesn't stop the board being fabricated, which is why it doesn't move the score.

Lists every component marked Do-Not-Place.

A sanity list so intentional omissions stay intentional. DNP is normal practice, so this never costs points.

A net carrying a real power-input pin (a placed power symbol — GND, +3V3, VCC, etc.) with no power-output source or PWR_FLAG anywhere on that net. Keyed on KiCad's own pin types, not the net name — an internal node like "12V_PHASE" or a plain enable signal like "CARRIER_PWR_ON" won't false-positive just because the name mentions voltage or power.

Usually a missing regulator connection or a forgotten PWR_FLAG. It's a schematic annotation with no physical consequence, so it's reported without costing points.

No TP* components anywhere in the design (skipped for schematics under 3 components).

Test points cost nothing on the schematic and save hours at the bench — but their absence doesn't stop anything, so it isn't scored.

Not one in-BOM component in the design carries a manufacturer, distributor, or internal catalogue identifier (e.g. a vendor's own library part-number scheme). Fires once per board, on the total-absence case only — partial coverage is normal mid-design and is left alone.

A schematic with no part numbers can't be quoted or ordered by anyone but the person who drew it, and an internal catalogue ID alone still only resolves inside that vendor's own systems — neither one is fully traceable to the outside world. KiCad's ERC has no equivalent check; nothing about missing part numbers stops a board routing or fabricating, which is also why this doesn't move the score.

A net whose pads aren't all actually bridged together by copper — the board's own ratsnest check. Layer-aware: two points at the same position on different copper layers are not connected unless a via or a through-hole pad sits there. Copper pours are modelled as connectivity, because ground and power pours are how most real boards join those nets. Two pads of the same net whose own copper physically overlaps also count as joined, with no track between them — a closed solder jumper, a shield-tab pad pair or a net-tied pad group is a real connection, not a break.

The schematic claims these pins are one net; the copper doesn't realise it yet.

A track, via or pad closer to the board outline than the minimum edge clearance. Non-plated mechanical mounting holes are excluded — there is no real copper there for the rule to apply to.

Copper right at the routed edge gets nicked or exposed when the panel is separated.

Two tracks on different nets, on the same copper layer, closer together than the minimum clearance — measured edge to edge, accounting for each track's own width. Track-to-track only; pad clearance is a much larger surface and is deliberately out of scope. See the limits note below.

Below the fab's clearance the two nets can bridge during etch.

Vias and through-hole pads whose annular ring, or drill diameter, falls below your board's own minimums. This one runs only when your project file actually supplies those rules: real boards range from 0.05mm to 0.3mm minimum annular width, so there is no defensible default and inventing one would be worse than staying silent.

Too little ring and the drilled barrel breaks out of its own pad at normal drill tolerance.

A power or ground net whose own traces vary a lot in width — some segments far narrower than the widest already routed on that same net. Compared against the net's own other traces, never against an external table. One finding per affected net, not one per thin segment.

A rule of thumb only, never a current-capacity calculation: real ampacity needs copper weight, ambient temperature and allowed temperature rise, none of which this tool has.

A through-hole pad with silkscreen graphics printed directly across its copper, reported once per pad. A footprint's own silk touching its own pads is a normal drawing convention and isn't flagged. Narrower than KiCad's own rule in two known ways: footprint text across a pad, and rectangle-shaped silk graphics, aren't covered here.

Ink on a solderable surface causes uneven wetting and is a common fab-house rejection, not a cosmetic nitpick.

An SMD pad containing exactly one via, centred strictly inside the pad's real shape. Scoped to exactly one via on purpose: a QFN/DFN thermal land carrying an intentional array of 8–12 stitching vias is a manufacturer-recommended pattern, and flagging it would make this check pure noise on ordinary boards.

A via in a land wicks solder paste away during reflow unless it is deliberately filled and capped. This tool reports the geometry only — it never claims to know whether a fill was specified, so check it against your fab request.

A pad whose solder-mask opening merges with a different-net neighbor's, or leaves no reliable web of mask between them — checked separately per side (front and back), using your board's own mask-expansion default and any per-pad or per-footprint override it declares. Pads on the same real net are never flagged, and a footprint your project explicitly allows to bridge internally is respected.

Once two adjacent pads' mask openings merge, solder can pool and bridge them during reflow — a real, common fab DFM rejection. Matched real KiCad DRC's own findings for this exact defect pad-for-pad on a real board with matching design rules. See the limits note below for where it still falls short.